Display device

ABSTRACT

The present invention provides a display device which has a narrow screen border, and excellent display equality. The display device according to the present invention comprises a display panel comprising a glass substrate and a source driver IC which is provided along the edge of the glass substrate. The FPC is connected between the source driver ICs. At the substrate end side of the source driver IC, a bump for GND, a bump for analog power supply, a bump for digital power supply, a bump for reference voltage at the positive polarity side, and a bump for reference voltage at the negative polarity side are formed sequentially from the outer side along the flow of current. These bumps for input and the FPC are connected with the lines for input on the glass substrate. The logic signal lines and are formed along the short side of the source driver IC and along the long side at the display area side.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a display device, and moreparticularly to a COG packaging type liquid crystal display comprisingan IC chip for driving a thin film transistor (TFT) on a glasssubstrate.

[0003] 2. Description of the Related Art

[0004] The liquid crystal display device is comprised of a liquidcrystal display panel which is further comprised of two substratesbetween which the liquid crystal layer is held, and a surface lightsource unit which is installed on the rear face side of the liquidcrystal display panel. The liquid crystal display panel is normallyconstructed by two insulation transparent substrates made of glass,which face each other, where display material, such as liquid crystals,is sandwiched, so that voltage is applied selectively to this displaymaterial. One of the substrates is a thin film transistor arraysubstrate (hereafter called TFT array substrate) where switchingelements, such as thin film transistors (TFT) and pixel electrodesconnecting these switching elements are formed in a matrix. The othersubstrate is a color filter substrate (CF substrate) which furthercomprises R, G and B color layers provided corresponding to the pixelelectrodes, and a black matrix (BM) provided between these color layers.

[0005] In the TFT array substrate, source lines and gate lines arecrossed via an insulation film to apply signals to the switchingelements. A plurality of source lines and gate lines are disposedrespectively, corresponding to the number of pixel electrodes. A COGtype liquid crystal device, where the IC chip for driving the pixelelectrodes is directly mounted on the substrate, is known (e.g. JapaneseUnexamined Patent Application Publication No. 2000-347206, 2000-81635and 2001-42282). This IC chip for driving is mounted at the end portionof the glass substrate, outside the display area of the substrate, viathe anisotropic conductive film (ACF). And FPC is connected to the endportion of the glass substrate, and power and signals are supplied tothe IC for driving via the lines provided on the glass substrate. Thebump configuration of the COG packaging type IC for driving will bedescribed with reference to FIG. 14. FIG. 14 is a top view depicting theconfiguration around the source driver IC, which is an IC for driving.The driver IC 101 is provided near the end portion of the glasssubstrate 27. At the longer side of the driver IC 101, a bump for output16 is provided, and at the other longer side bumps for input areprovided. The bump for output 16 is provided at the display area 34 sideon the glass substrate, and the bumps for input are provided at the endportion of the substrate. The bumps for input are GND 1, bump for analogpower supply 2, bump for digital power supply 3, bump for referencevoltage at the positive polarity side 4 and bump for reference voltageat the negative polarity side 5. A plurality of the driver ICs 101 aredisposed on the glass substrate, outside the display area, and FPCs(Flexible Printed Circuit) 21 are connected to the end portion of thesubstrate corresponding to the respective driver IC 101. On the side ofthe driver IC 101, cascade line is formed, by which a plurality ofdriver ICs are sequentially connected. This configuration, however, hasthe following problems.

[0006] Because of the dispersion of the ACF connections between thebumps for input of the driver IC 101 and the lines on the glasssubstrate, the resistance value tends to increase. Also many bumps forconnection must be provided on the driver IC, so the bump configurationis restricted and the pitch between bumps cannot be freely increased.Therefore the pitch of the signals of the FPC 21 becomes large withrespect to the pitch of the bumps for input of the driver IC 101, linesfrom the FPC 21 to the driver IC 101 become thin, and the lineresistance value increases. By such an increase in the resistancebetween bumps and the FPC, the driver IC 101 may not operate normally orthe desired voltage may not be output. And the operation of the driverIC may have problems, which decreases the display quality. Also in thecase of a COG packaging type, the screen border size increases.

[0007] In this way, in the case of a conventional COG packaging typeliquid crystal display device, the screen border size becomes big andthe display quality drops if FPC to the driver IC is wired on the glasssubstrate.

SUMMARY OF THE INVENTION

[0008] With the foregoing in view, it is an object of the presentinvention to provide a display device which can decrease the screenborder size and has excellent display quality.

[0009] To these ends, according to one aspect of the present invention,there is provided a display device, including a display panel having aninsulation substrate; a drive circuit disposed around a display area onthe insulation substrate to output signals to the display panel; aplurality of bumps formed on the drive circuit; and a plurality of linesformed on the insulation substrate and connected with the bumps, whereinadjacent two or more of the plurality of bumps are electricallyconnected on the drive circuit, and the electrically connected two ormore bumps are connected with one of the lines via an anisotropicconductive film. This can reduce the connection resistance between linesand bumps.

[0010] In the above display device, it is preferred that the drivecircuit is disposed along an edge of the insulation substrate, and theelectrically connected bumps are formed substantially in parallel withthe edge. This can increase the width of the input line on a glasssubstrate, thereby reducing line resistance.

[0011] In the above display device, the drive circuit may be disposedalong an edge of the insulation substrate, and the electricallyconnected bumps may be formed substantially perpendicular to the edge.This can reduce the connection resistance without increasing a drivecircuit size.

[0012] According to one aspect of the present invention, there isprovided a display device, including a display panel having aninsulation substrate; a plurality of drive circuits disposed with aspace at an end portion of the insulation substrate along an edge of theinsulation substrate to output signals to the display panel; a linesection placed at the end portion of the insulation substrate, betweenthe plurality of drive circuits, having external lines for supplyingsignals or power to the plurality of drive circuits; and a plurality ofinput lines formed on the insulation substrate and connected withcorresponding lines of the plurality of external lines. This can reducethe screen border area.

[0013] In the above display device, the external line corresponding tothe input line for a highest current flow of the plurality of inputlines is preferably placed at a very side of the line section. This canreduce an output error.

[0014] In another aspect of the above display device, the drive circuitmay have a plurality of bumps for input formed at an edge side of theinsulation substrate along the edge and connected with a linecorresponding to the plurality of input lines, and a bump for inputcorresponding to an input line for a highest current flow of theplurality of input lines may be placed at an outermost side of the drivecircuit. This can prevent a decrease in display quality due to longline.

[0015] In the above display device, it is preferred that the bumps forinput include a bump for GND, a bump for power supply and a bump forreference voltage, the bump for GND and the bump for power supply areplaced as one block at a side section and a center of the drive circuit,and the bump for reference voltage is disposed between blocks. This canreduce manufacturing costs.

[0016] In the above display device, the bump for GND and the bump forpower supply may be electrically connected with the bump for GND and thebump for power supply in a different block, respectively, in the drivecircuit. This can reduce the number of lines.

[0017] In the above display device, the bump for GND or the bump forpower supply in one block may be electrically connected two rows ofbumps. This can reduce the connection resistance.

[0018] In the above display device, the line section may be disposed atevery other space between the drive circuits, and the line section maybe connected with the bumps for input of the drive circuits on bothsides. This can reduce the number of connection points in the lines.

[0019] According to one aspect of the present invention, there isprovided a display device, including a display panel having aninsulation substrate; a plurality of drive circuits disposed with aspace along an edge of the insulation substrate to output signals to thedisplay panel; cascade lines formed on the insulation substrate toconnect the drive circuits next to each other; and a plurality of bumpsfor cascade line formed on the drive circuit along a side to a displayarea and a side to an adjacent drive circuit and connected with theplurality of cascade lines. This can increase the bump area of thesource driver IC.

[0020] In the above display device, it is preferred that the cascadelines include a clock signal line and a plurality of image data signallines, and the clock signal line is disposed between the plurality ofimage data signal lines. This can reduce a difference in the distance ofa clock signal and a plurality of image data signals to reduce imagedata loading error.

[0021] The above display device may further include bumps for outputformed along a side of the drive circuit close to a display area tooutput signals to the display panel, and the bumps for output or bumpsfor a cascade line may be placed in a staggered fashion. This canincrease the area for bumps.

[0022] The above and other objects, features and advantages of thepresent invention will become more fully understood from the detaileddescription given hereinbelow and the accompanying drawings which aregiven by way of illustration only, and thus are not to be considered aslimiting the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a top view depicting a configuration of the liquidcrystal display panel;

[0024]FIG. 2 is a plan view depicting a configuration of the end portionof the liquid crystal display panel of the liquid crystal display deviceaccording to the first embodiment of the present invention;

[0025]FIG. 3 is a plan view depicting a configuration of the sourcedriver IC of the liquid crystal display device according to the firstembodiment of the present invention;

[0026]FIG. 4 is a plan view depicting a configuration of the bumps forGND provided on the source driver IC of the liquid crystal displaydevice according to the first embodiment of the present invention;

[0027]FIG. 5 is a plan view depicting a configuration of the bumps forreference voltage provided on the source driver IC of the liquid crystaldisplay device according to the first embodiment of the presentinvention;

[0028]FIG. 6 is a plan view depicting another configuration of the bumpsfor reference voltage provided on the source driver IC of the liquidcrystal display device according to the first embodiment of the presentinvention;

[0029]FIG. 7 is a plan view depicting a configuration of an area aroundthe bumps for input provided on the source driver IC of the liquidcrystal display device according to the first embodiment of the presentinvention;

[0030]FIG. 8 is a plan view depicting a configuration of an area aroundthe bumps for logic signals provided on the source driver IC of theliquid crystal display device according to the first embodiment of thepresent invention;

[0031]FIG. 9 is a plan view depicting another configuration of an areaaround the bumps for logic signals provided on the source driver IC ofthe liquid crystal display device according to the first embodiment ofthe present invention;

[0032]FIG. 10 is a plan view depicting a configuration of an area aroundthe bumps for input provided on the source driver IC of the liquidcrystal display device according to the second embodiment of the presentinvention;

[0033]FIG. 11 is a plan view depicting a configuration of an area aroundthe bumps for input provided on the source driver IC of the liquidcrystal display device according to the third embodiment of the presentinvention;

[0034]FIG. 12 is a plan view depicting a configuration of the endportion of the liquid crystal display panel of the liquid crystaldisplay device according to the fourth embodiment of the presentinvention;

[0035]FIG. 13 is a plan view depicting a configuration of an area aroundthe bumps for input provided on the source driver IC of the liquidcrystal display device according to the fourth embodiment of the presentinvention; and

[0036]FIG. 14 is a plan view depicting a configuration of an area aroundthe bumps for input provided on the source driver IC of a conventionalliquid crystal display device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] First Embodiment

[0038] Embodiments of the present invention will now be described withreference to the accompany drawings. The following description shows thepreferred embodiments of the present invention, however the scope of thepresent invention is not limited by the following embodiments. In thefollowing description, composing elements denoted with a same referencesymbol substantially have the same content.

[0039] The configuration of the liquid crystal display panel 33 of theliquid crystal display device will now be described with reference toFIG. 1. FIG. 1 is a top view depicting the configuration of the liquidcrystal display panel in the COG packaging type liquid crystal displaydevice. The liquid crystal display panel 33 shown in FIG. 1 is comprisedof a display area 34 which is further comprised of a plurality of pixelsarrayed in a matrix, and a screen border area 35 outside of the displayarea 34. The liquid crystal display panel 33 is comprised of an arraysubstrate where an array circuit is formed and the counter substratethereof, and the liquid crystals are sealed between these twosubstrates. The active matrix type liquid crystal display panel hasswitching elements for each pixel to control the input/output of displaysignals. A typical switching element is a TFT (Thin Film Transistor).

[0040] The color liquid crystal display device has an RGB color filterlayer on the counter substrate. Each pixel of the display area of theliquid crystal display panel 33 displays one of the colors R, G and B.Of course in a monochrome display, each pixel displays either black orwhite. In the display area in the array substrate, a plurality of sourcelines and gate lines are disposed in a matrix. The source lines and thegate lines cross roughly to be perpendicular to each other, and a TFT isdisposed near the intersection. In the screen border area 35 of theliquid crystal display panel, a plurality of rectangular source driverICs 101 are provided in a row along one side of the substrate. At theend portion of the substrate of the side perpendicular to the side wherethe source driver IC 101 is provided, a plurality of gate drivers 111are provided in a raw in the same way. The row where the source driverICs 101 are provided and the row where the gate driver ICs 111 areprovided are perpendicular to each other. One side of the substratewhere the source driver ICs 101 are provided is regarded as the edge ofthe substrate.

[0041] On the rear face side of this liquid crystal display panel 33, asurface light source device comprising a light source, light guidingplate and optical sheet is disposed. The liquid crystal panel 33 has aliquid crystal layer which is sandwiched by the TFT array substrate andthe CF substrate. On the display area 34 of the TFT array substrate,switching elements for driving the liquid crystal layer are formed in amatrix. Also a plurality of gate lines and a plurality of source linesare provided to be perpendicular to each other for supplying signals tothe switching elements. The source driver ICs 101 and the gate driverICs 111 are installed on the glass substrate via the anisotropicconductive film ACF.

[0042] On the bottom face of each driver IC, bumps for input is formedto connect with the terminal of the lines formed on the glass substrate.These bumps for input and the terminals of the lines are electricallyconnected via the anisotropic conductive film. From the control circuitsection 36, image data signals, clock signals and power supply fordriving ICs are supplied to the gate driver IC 111 and the source driverIC 101 via the FCP and the lines on the glass substrate. Signals fromeach driver IC are supplied to the gate lines and the source lines todrive the switching elements, and voltage is supplied to the pixelelectrodes to drive the liquid crystal layer and display a desiredimage.

[0043] The configuration of the source driver IC of the liquid crystaldisplay device according to the present embodiment will now be describedwith reference to FIG. 2 to FIG. 9. 1 is a bump for GND, 2 is a bump forthe analog power supply, 3 is a bump for the digital power supply, 4 isa bump for the reference voltage at the positive polarity side, 5 is abump for the reference voltage at the negative polarity side, 6 is abump for the analog power supply, 7 is a bump for GND, 8 is a bump forthe digital power supply, 9 is a bump for the reference voltage at thepositive polarity side, 10 is a bump for the reference voltage at thenegative polarity side, 11 is a bump for the digital power supply, 12 isa bump for the analog power supply, 13 is a bump for GND, 14 is a bumpfor the digital signal, 15 is a bump for the digital signal, and 16 is abump for the output. These are provided on the source driver IC 101. 17is a control signal line, 18 is an image data signal line, 19 is animage data signal line and 20 is a clock signal line. These are logicsignals which are cascade-connected between the source driver IC 101 aand the adjacent source driver IC 101 b. 22 is a reference voltage atthe positive polarity side, 23 is an analog voltage, 24 is GND, 25 is adigital power supply and 26 is a reference voltage at the negativereference side. These are lines between the FPC 21 and the source driverIC 101. 60 is cascade lines and 61 is lines for input, and these areformed by patterning a metal film, a transparent conductive film such asITO, on the glass substrate.

[0044]FIG. 2 is a plan view depicting the configuration of the endportion of the substrate where the source driver IC 101 of the liquidcrystal panel 33 is provided. As FIG. 2 shows, the source driver ICs 101according to the present embodiment are provided on the screen borderarea 35 along the edge of the substrate. Here it is assumed that thescreen border area where the source driver ICs 101 are provided iscalled the end portion of the substrate. The long side 102 of therectangular source driver IC 101 a is in parallel with the substrateedge. The long side 103 at the opposite side is roughly in parallel withthe display area 34. It is assumed that the long side 102 is the longside 102 at the substrate end side, and the long side 103 is the longside 103 at the display area side. At the short side 104 side of thesource driver IC 101 a, the source driver IC 101 b is provided with aspace. These source drivers ICs 101 are continuously disposed in a rowwith a space along one side of the substrate. The cascade line for logicsignals 60 for cascade connection is formed in the space between thesource driver ICs on the glass substrate, and each source driver IC 101is cascade-connected. Between the adjacent source driver IC 101 a andthe source driver IC 101 b, the FPC 21, for supplying signals and powerfrom the external control circuit section 36, is installed from thesubstrate end side. By this, the screen borer area can be narrower. Onthe FPC 21, GND line, line for the digital power supply, line for theanalog power supply, line for the reference voltage at the positivepolarity side, and line for the reference voltage at the negativepolarity side, a total of five types are formed for driving the sourcedriver ICs 101. These five types of lines on the FPC are connected tothe corresponding lines of the lines for input 61 respectively. Thesignals and the power from the FPC 21 are supplied to the source driverIC 101 via the lines for input 61 formed on the glass substrate. For thelines for input 61 and the cascade lines 60, a plurality of lines areformed on the glass substrate respectively.

[0045] In order to decrease the influence of line resistance of thecascade line 60 and in the line for input 61 on the glass substrate ondisplay quality deterioration, it is preferable to make the line lengthshorter and the line width thicker. On the bottom face of the sourcedriver IC 101 at the substrate end side, bumps for input for inputtingsignals and power from FPC are provided. At the display area side of thesource driver IC 101, a bump for output for outputting signals to thesource line is formed. These bumps for input are connected to thecorresponding terminals of the line for input 61 on the glass substratevia the ACF. The bumps for output are connected with the correspondingsource lines provided in the display area. When the FPC 21 is connectedbetween the source driver ICs as mentioned above, the line resistancemust be decreased by increasing the line width on the glass substrate,since the line length becomes longer. This configuration will bedescribed with reference to FIG. 3.

[0046] At first, the bump array of the source driver IC 101 will bedescribed. FIG. 3 is a plan view depicting the bump array of the sourcedriver IC of the liquid crystal display device according to the presentembodiment. As FIG. 3 shows, the bumps for GND 1, 7 and 13, the bumpsfor analog power supply 2, 6 and 12, the bumps for digital power supply3, 8 and 11, the bumps for reference voltage at the positive polarityside 4 and 9, and the bumps for reference voltage at the negativepolarity side 5 and 10 are provided in two rows along the long side 102at the substrate end side of the source driver IC 101. By these bumpsfor input, signals from the FPC are input. The bump for GND 1, the bumpfor GND 7 and the bump for GND 13 are electrically connected inside thesource driver IC. In the same way, the bump for analog power supply 2,the bump for analog power supply 6, the bump for analog power supply 12,the bump for digital power supply 3, the bump for digital power supply 8and the bump for digital power supply 11 are also electrically connectedinside the source driver IC. Low resistance line is used for theseconnections. The bump for GND 1, the bump for analog power supply 2, andthe bump for digital power supply 3 form one block, and this block isprovided at the left side of the source driver IC 101. In the same way,the bump for GND 7, the bump for analog power supply 6, and the bump fordigital power supply 8 form one block, and this block is provided at thecenter of the source driver IC 101. Also the bump for GND 13, the bumpfor analog power supply 12, and the bump for digital power supply 1 formone block, and this block is provided at the right of the source driverIC 101. And between each block, the bump for reference voltage at thepositive polarity side 4 and the bump for reference voltage at thenegative polarity side 5, or the bump for reference voltage at thepositive polarity side 9 and the bump for reference voltage at thenegative polarity side 10 are provided. In this way, five types of bumpsfor input are formed in one source driver IC 101.

[0047] The bump for digital signal 14 and the bump for digital signal 15are provided around the corner of the display area side of the sourcedriver IC 101. The bumps for digital signals 14 and 15 are bumps forcascade connection, which have bi-directional functions. In other words,when the digital signal is input to the bump for digital signal 15, thebump for digital signal 14 outputs the output signal to the next sourcedriver IC. Whereas when the digital signal is input to the bump fordigital signal 14, the bump for digital signal 15 outputs the outputsignal to the next source driver IC. Here the digital signal is input tothe bump for digital signal 14, and is output from the bump for digitalsignal 15. This connection is continuously made between adjacent sourcedriver ICs to forme a cascade connection. Therefore the bump for digitalsignal 14 becomes upstream, and the bump for digital signal 15 becomesdownstream. A plurality of bumps for digital signals 14 and 15 areprovided along the long side 103 at the display area side and along theshort side 104 of the adjacent drive circuit side respectively.

[0048] At the long side 103 side of the display area of the sourcedriver IC 101, bumps for output 16 are provided. A plurality of bumpsfor output 16 are provided along the long side 103 between the bumps fordigital signal 14 and the bumps for digital signal 15. The bumps foroutput 16 are connected to the respective source line, and outputs thepixel voltage in the TFT of the liquid crystal display panel 33. In FIG.3, the number of bumps for reference voltage at the positive polarityside 4 and 9, and the bumps for reference voltage at the negativepolarity side 5 and 10 is one each, but actually the number of bumps atthe positive polarity side and the negative polarity side is m/2respectively, since m/2 out of m (m is 2 or higher integer) of thevoltage lines, which are input from the outside which determines thereference of the source driver IC 101, are the voltage lines at thepositive polarity side, and, the other m/2 are the voltage lines at thenegative polarity side. The number of lines thereof is of course m/2.Also m/2 number of bumps for input are provided at the substrate endside and the inside thereof in two rows. For the bumps for output 16,bumps for digital signal 15 and bumps for digital signal 14 as well, aplurality of bumps are provided corresponding to the number of sourcelines. The source driver IC 101 is driven by the power supply voltage,which is input from the bump for digital power supply and the bump foranalog power supply, and outputs the image display signals to the liquidcrystal display panel based on such digital signals as clock signals,image data and control signals, and reference voltage.

[0049] The configuration of these bumps will now be described withreference to FIG. 4. FIG. 4 is a plan view depicting the configurationof the bump for GND 1. The bump for GND 1 is comprised of many bumps, 50a and 50 b. The bump for GND 1 is comprised of two rows of bumps, thatis a row of bumps 50 b, at the substrate end side, and a row of bumps 50a, provided inside the bumps 50 b, and each row is in parallel with thelong side 102 of the source driver IC 101. Therefore the row of bumps 50a at the display area side and the row of bumps 50 b at the substrateend side are in parallel with the substrate edge. At the respectiveportion of the bumps 50 a and 50 b, conductive material, such as gold,is exposed, surrounded by an insulation material. For forming thesebumps, a normal manufacturing method is used, such as patterning theconductive material, then coating the insulation material, and exposingand developing this to provide holes, and then plating. All the bumps 50a and 50 b are connected with a low resistance conductive material, andall the bumps 50 a and 50 b are at a same potential. The bumps 50 a and50 b are formed on the source driver IC 101, and are connected with thelines on the glass substrate via an anisotropic conductive film (ACF).

[0050] Since the line width and the line length on the glass influencethe line resistance, it is preferable to make the line width as wide aspossible. In particular when the line is made of a transparentconductive film, such as ITO, of which the electric characteristics arenot as good as metal, the deterioration of line resistance appears moreclearly. By forming many bumps 50 b along the substrate end, as shown inthe present embodiment, the line width can be widened up to the lengthof the row of the bumps 50 b. If the exposed area of the conductivematerial of the bumps 50 a and 50 b is increased, the uniformity of theexposed faces deteriorates, and the surface of the exposed faces becomeuneven, this due to manufacturing reasons. This makes the connectionresistance between the ACF and the bump higher. The ACF is normallyconstituted by mixing conductive materials in resin film. Even if thedistribution of the particles in the ACF disperses, the deterioration ofthe connection resistance can be prevented by providing many bumps witha same potential and connecting them with the ACF. If the number ofcontact points with the ACF is increased by providing a plurality ofbumps to be connected with one line, a decrease in the connectionresistance can be prevented, since even if certain bumps have connectionproblems, other bumps can be in connection. By connecting two or moreadjacent bumps at a same potential with one line inside the sourcedriver IC 101, the resistance value can be decreased, and the generationof display defects caused by the resistance deterioration can beprevented.

[0051] The other bumps for GND 7 and 13, are also comprised of aplurality of bumps respectively in the same way. The bumps for analogpower supply 2, 6 and 12 and the bumps for digital power supply 3, 8 and11 are also comprised of a plurality of bumps respectively in the sameway, so a similar effect can be obtained. Certainly the respectivenumber of bumps to be connected to one line may be a different number,and the length of the row of the bumps can be adjusted corresponding tothe width of the line.

[0052] Now the configuration of the bump for reference voltage at thepositive polarity side 4 will be described with reference to FIG. 5. Inthe reference voltage line, less current flows compared with the powersupply and GND line, so display quality is less influenced, even if thenumber of bumps for reference voltage is less than the number of bumpsof the bumps for GND, the bumps for analog power supply and the bumpsfor digital power supply. Therefore in the present embodiment, the bumpsfor reference voltage 4 are comprised of two rows, where two bumps areelectrically connected. As FIG. 5 shows, the bumps 50 b are provided atthe substrate end side, and the bumps 50 a are provided along with thebumps 50 b, at the inner side of the substrate (display area side). Theadjacent bumps 50 a and 50 b are electrically connected. These bumps 50a and 50 b constitute a set of bumps, and are connected to one of thereference voltage lines at the positive polarity side. Next to thesebumps 50 a and 50 b, the bumps 51 a and 51 b are provided, which arealso electrically connected. These adjacent bumps 51 a and 51 bconstitute a set of bumps, in the same way, and are connected to adifferent reference voltage line. This is the same for the bumps 52 aand 52 b. The bumps 50 a, 51 a and 52 a are formed in a row along thesubstrate end. In the same way, the bumps 50 b, 51 b and 52 b are alsoformed in a row along the substrate end. In this way, among the bumpsarrayed in two rows, two bumps, as a set, are connected with therespective reference voltage line. Therefore the bumps 50 a, 51 a and 52b are insulated respectively.

[0053] The bumps 50 a and 50 b are formed on the source drive IC 101,and are connected to one line for the positive reference voltageprovided on the glass substrate via an anisotropic conductive film(ACF). Since bumps are provided for the bumps for reference voltage atthe positive polarity side 4 in an actual source driver IC 101,corresponding to the positive reference voltage lines, the number ofbumps in a row is m/2, and two rows are formed along the substrate end.In other words, m/2 sets of bumps are provided corresponding to thepositive reference voltage lines, and two rows of these are formed, so atotal of m bumps are provided. And two bumps at a same potential areprovided in a direction perpendicular to the substrate end. By providingthe plurality of bumps in a vertical direction, the number of bumps tobe connected with one line can be increased without increasing theexternal size of the source driver IC 101. Therefore the connectionresistance can be decreased.

[0054] Just like the bumps for reference voltage at the positivepolarity side 4, for the bumps for reference voltage at the negativepolarity side 5, bumps for reference voltage at the positive polarityside 9, and bumps for reference voltage at the negative polarity side 10as well, m/2 number of bumps are provided for one row, and two rows ofthese bumps are provided to be perpendicular to the substrate end. Andtwo bumps at the substrate end side and inner side thereto, as one set,are connected with the input terminal of one line on the glasssubstrate. By this a similar effect can be obtained. Needless to say,not only the source driver IC 101 but also the bumps of the gate driverIC 111, the bumps for output, and the bumps for digital signals may beformed as the configuration shown in FIG. 4 and FIG. 5 to obtain asimilar effect.

[0055] In FIG. 5, two bumps are provided vertically, but if it isnecessary to reduce the line resistance value, then two bumps with asame potential may be provided in a horizontal direction (in a paralleldirection with the substrate edge), as shown in FIG. 6. In this case,the m number of bumps are formed in one row along the substrate end. Andtwo adjacent bumps (e.g. bumps 50 a and 50 b) are electrically connectedas one set, and m/2 sets of bumps with a same potential are formed. Aset of bumps with a same potential are connected with the respectivereference voltage on the glass substrate via the ACF. With thisconfiguration as well, the effect of providing a plurality of bumps canbe acquired. Also if a set of bumps are constituted along the substrateend, as shown in FIG. 6, line on the glass substrate can be thicker.This makes it possible to reduce the line resistance value and toimprove the display quality.

[0056] Now the configuration where the FPC 21 is connected to thesubstrate end of the glass substrate 27, on which the above mentionedsource driver IC 101 is mounted, will be described with reference toFIG. 7. FIG. 7 is a plan view depicting the configuration of the sourcedriver IC 101 and the FPC 21 on the glass substrate. The FPC 21 isconnected between the source driver IC 101 a and the adjacent sourcedriver IC 101 b. The FPC 21 is connected from the substrate edge betweenthe source driver ICs, and is disposed at the substrate end side fromthe long side 103 of the source driver IC 101 at the display area side.For packaging purposes, the FPC 21 and the glass substrate must beconnected at a distance that is a predetermined length or more, sonarrowing the screen border of the substrate is limited. By disposingthe FPC 21 between the source driver ICs 101 as shown in the presentembodiment, the FPC can be formed more to the inner side of the glasssubstrate 27 than the case of disposing the source driver IC 101 and theFPC facing each other, and disposing the FPC to the outer side from thelong side of the substrate end of the source driver IC 101, which canmake the screen border narrower.

[0057] The source driver IC 101 has a similar configuration as thatshown in FIG. 3. Now the configuration and the connection between thesource driver ICs 101 a and 101 b and the FPC 21 a will be described.The FPC provided between the source driver IC 101 a and the adjacentsource driver IC 101 b is regarded as FPC 21 a, and the FPC 21 providedbetween the source driver IC 101 b and the adjacent source driver IC 101c is regarded as FPC 21 b. FPC 21 a and 21 b and the source driver ICs101 a, 101 b and 101 c have the same configuration respectively, and areconnected in the same way, so description is omitted for theconfiguration around the FPC 21 b. This source driver IC 101 and the FPC21 are mounted repeatedly along the substrate end. In the FPC 21, aplurality of external lines for supplying power supply and signals fromthe control circuit section 36 are provided. These external lines arefor GND, analog power supply, digital power supply, reference voltage atthe positive polarity side, and reference voltage at the negativepolarity side. Near the tip of the FPC 21, the terminal for GND 24 c,the terminal for analog power supply 23 c, the terminal for referencevoltage at the positive polarity side 22 c, the terminal for referencevoltage at the negative polarity side 26 c and the terminal for digitalpower supply 25 c are provided for connecting the lines on the FPC andthe lines for input on the glass substrate. On the glass substrate,lines for GND 24 d, analog power supply 23 d, digital power supply 25 d,reference voltage at the positive polarity side 22 d, and referencevoltage at the negative polarity side 26 d, which are lines for inputfrom the terminal to the bumps for input, are provided in parallel withthe substrate edge. These lines for input are connected with thecorresponding bumps for input respectively, crossing the side section ofthe FPC (side perpendicular to the substrate edge). For example, theterminal for analog power supply 23 c is connected with the bump foranalog power supply 22 b provided on the source driver IC 101 b via theanalog power supply 23 d on the glass substrate. The input lines for theGND 24 d, digital power supply 25 d, reference voltage at the positivepolarity side 22 d, and reference voltage at the negative polarity side26 d as well are connected in the same way.

[0058] In the present embodiment, the terminal for digital power supply25 c, the terminal for analog power supply 23 c and the terminal for GND24 c of the FPC 21 a are connected to the bump for digital power supply3 b, the bump for analog power supply 2 b, and the bump for GND 1 b inthe block at the left of the source driver IC 101 b provided at theright of the FPC 21 a respectively. The terminal for reference voltageat the positive polarity side 22 c and the terminal for referencevoltage at the negative polarity side 26 c of the FPC 21 a, on the otherhand, are connected to the bump for reference voltage at the positivepolarity side 9 a and the terminal for reference voltage at the negativepolarity side 10 a of the source driver IC 101 a provided at the left ofthe FPC 21 a respectively. In this way, signals or power are supplied toboth the source driver IC 101 a and the source driver IC 101 b from theFPC 21 a at one location. By repeating such a configuration, power andsignals are supplied to all the source driver ICs 101 formed at the endportion of the substrate.

[0059] When the FPC 21 is disposed between the source driver ICs, thelines on the glass substrate are formed in parallel with the substrateend. Therefore the thickness and the number of lines provided outsidethe source driver IC 101 must be restricted in order to decrease thescreen border area. By connecting the lines from the FPC 21 a at onelocation with the bumps for input of the source driver IC 101 a and thesource driver IC 101 b at the right and left to supply signals andpower, as the present embodiment shows, the width of the space wherelines can be formed can be increased without widening the screen borderarea. As a result, the lines can be thicker even if the FPC is connectedbetween the source driver ICs, and a drop of the display quality due tothe deterioration of the line resistance can be suppressed.

[0060] Normally the current that flows to the line of GND, the lines ofdigital power supply and the analog power supply of the power supplysystem is larger than the current which flows through the lines of thereference voltage, which is a signal system. In order to suppress a dropof display quality due to the deterioration of the line resistance, itis preferable to make the lines of the GND 24 d, the digital powersupply 25 d and the analog power supply 23 d to be thick or short. Forthe line for the reference voltage, on the other hand, where the currentflow is small, the line may be thinner than those of the GND and thepower supply system, because the influence on the display quality issmall. In order to make the lines of the GND and the power supply systemthick, the lines for GND, digital power supply and analog power supplyare connected with the source driver IC 101 b at the right, and thelines for reference voltage, where there are many lines by where theinfluence is small even if the line is thin, is connected with the bumpsfor reference voltage 9 a and 11 a of the source driver IC 101 a at theleft. By connecting many lines of the reference voltage and the lines ofthe GND, the analog power supply and the digital power supply areconnected separately to the source driver ICs 101 at the left and right,so in this way the lines of the GND, analog power supply and digitalpower supply on the glass substrate can be thicker, and the drop ofdisplay quality due to the deterioration of the line resistance can beprevented.

[0061] The current that flows through lines is normally highest for theGND, then the analog power supply and finally the digital power supply,where the total current that flows through the lines for the analogpower supply and the digital power supply is roughly the same as thecurrent that flows through the line for the GND. In the presentembodiment, the terminal for GND 24 c, the terminal for analog powersupply 23 c and the terminal for digital power supply 25 c are providedin this sequence from the outer side, at the right of the FPC 21 a. Inthe source driver IC 101 b, on the other hand, the bump for GND 1 a, thebump for analog power supply 2 a and the bump for digital power supply 3a are provided in this sequence from the outer side, at the left of thelong side 102 at the substrate end side. By this configuration, the linelength on the glass substrate can be shorter and the line resistancevalue can be smaller as the current which flows increases so that avoltage drop can be suppressed. As a result, output errors of the sourcedriver IC can be eliminated.

[0062] Also the size of the bumps for input can be changed according tothe thickness of the line. In other words, the number of bumps 50 a isadjusted for the line for the GND, where the highest current flows, sothat the length of the row of the bumps 50 a shown in FIG. 4 becomeslonger. For the line for the analog power supply, where the secondhighest current flows, the number of bumps is decreased so that the rowthereof becomes shorter than the row of the bumps for GND. For the linefor the digital power supply, where the third highest current flows, thenumber of bumps is further decreased. In this way, by adjusting thenumber of bumps to increase the thickness of the lines according tocurrent flow, and by increasing the size of the bumps according to thethickness, line resistance can be decreased without increasing thepackaging space. Also the connection resistance can be decreased byincreasing the number of bumps for input to be connected with one line.By this, a liquid crystal display device which excels in display qualityand has a narrow screen border area can be provided.

[0063] The logic signal lines 17, 18 and 19, which are cascade-connectedbetween the source driver IC 101 a and the source driver IC 101 b, areprovided at the long side at the display area side and at the short sideat the source driver IC side. The logic signal lines between the sourcedriver IC 101 b and the source driver IC 101 c also have a similarconfiguration, so illustration and description thereof are omitted. Theconfiguration of the above mentioned cascade-connected logic signallines will now be described with reference to FIG. 8. In the sourcedriver IC 101 a according to the present embodiment, a bump for digitalsignals 15 a is formed in an area near the corner at the right at thedisplay area side. A plurality of image data signal lines 18 and 19 andcontrol signal lines 17 are provided respectively corresponding to thenumber of colors of the liquid crystal display panel. In the same way,the bump for digital signals 14 b is formed in an area near the cornerat the left at the display area side in the source driver IC 101 b. Inthis bump for digital signals 15 a, a plurality of bumps are formedalong the long side 103 and short side 104 at the display area side. Inthe same way, in the bump for digital signals 14 b, a plurality of bumpsare formed along the long side 103 and short side 104 at the displayarea side. The plurality of bumps of the bumps for digital signals 15 aand the bumps for digital signals 14 b are formed symmetrically, andrespective bumps correspond to each other by the image data signal lines18 and 19, control signal line 17 and clock signal line 20.

[0064] The source driver IC upstream (e.g. source driver IC 101 a) tothe source driver IC downstream (e.g. source driver IC 10 b) aresequentially cascade-connected by the logic signal lines. The logicsignal lines to be cascade-connected used to be formed along the longside 102 at the substrate end side, which restricts the size of thebumps for input. Therefore unless the source driver IC size isincreased, the lines to be connected to the bumps become narrow, whichdeteriorates resistance. Also if the FPC 21 is connected between thesource driver ICs when the logic signal line is formed along the longside 102 at the substrate end side, the bumps for input become closer tothe center of the source driver IC than the bumps for logic signals,which makes the lines to be connected to the bumps for input on theglass substrate longer. If each one of the bumps for digital signals 14and the bumps for digital signals 15 is formed along two sides, the longside 103 and the short side 104, at the display area side, as in thisembodiment, the area for forming the bumps of the source driver IC canbe increased, and the line resistance can be decreased. Each one of thebumps for digital signals 14 may be laid out zigzag. This allows anincrease in the bump size without increasing the source driver IC size.In the same way, the bumps for digital signals 16 and the bumps foroutput may be laid out zigzag.

[0065] In FIG. 9, the control signal line 17 and the image data signalline 18 are connected to the bumps for logic signals 15 a, which areprovided at the long side 103 at the display area side of the sourcedriver IC 101 a. At the short side 104 side of the source driver IC 101a, the image data signal line 19 and the clock signal line 20 areprovided. The total number of image data signal lines 18 and 19 is n (nis 2 or higher integer) according to the number of colors. The number ofimage data signal lines 18 is n/2, and the number of image data signallines 19 is n/2. In this configuration, however, a difference isgenerated in the distances between each one of the n number of imagedata signal lines and the clock signal line. If there is a difference inthe distances between each image data signal line and the clock signalline, image data capturing errors may be generated by delays andwaveform distortion, due to the line resistance value of the image datasignal lines.

[0066] In this case, the difference in the distances between each imagedata signal line and clock signal line can be decreased by disposing theclock signal line 20 at the center, between n/2 number of image datasignal lines 18 and n/2 number of image data signal lines 19, as shownin FIG. 8. In FIG. 8, the bump for digital signals 15 a, provided at thelong side 103 side (display area side) of the source driver IC 101 a, isconnected with the bump for digital signals 14 b, provided at the longside 103 side (display area side) of the source driver IC 101 b via thecontrol signal line 17 and the image data signal line 18. In the sameway, the bump for digital signals 15 a, provided at the short side 104side of the source driver IC 101 a, is connected with the bump fordigital signals 14 b, provided at the short side 104 side of the sourcedriver IC 101 b via the clock signal line 20 and the image data signalline 19. Here it is assumed that the adjacent source driver IC side ofthe source driver IC 101 is a side section. And the clock signal line 20is formed at the center between the image data signal line 19 and theimage data signal line 18. By disposing the clock signal line at thecenter of all the image data signal lines, data capturing errors causedby delays and waveform distortion due to the line resistance value onthe glass substrate can be decreased. Also by transmitting the controlsignals, which speed is low, outside the image data signal line, thedifference in glass line resistance values of the clock signal and theimage data signal can be decreased, which makes it easier to securemargins for setup and hold time. In this way, a liquid crystal displaydevice with excellent display quality can be provided by disposing theclock signal line 20 between the image data signal line 18 and the imagedata signal line 19.

[0067] Second Embodiment

[0068] The present embodiment will be described with reference to FIG.10. FIG. 10 is a plan view depicting the configuration of the areaaround the bumps for input provided on the source driver IC of theliquid crystal display device. Compared with the first embodiment, theconfiguration between the FPC 21 and the bumps for input is different inthe present embodiment, and description will be omitted for theconfiguration the same as the first embodiment.

[0069] In the present embodiment, in the FPC 21, the terminal for GND 24c and the terminal for analog power supply 23 c are connected to thesource driver IC 101 b at the right, and the terminal for digital powersupply 25 c, the terminal for reference voltage at the positive polarityside 22 c and the terminal for reference voltage at the negativepolarity side 26 c are connected with the source driver IC 101 a at theleft. By providing the terminal for digital power supply 25 c at theleft of the FPC 21, the line width of the GND 24 d and the analog powersupply 23 d can be increased without increasing the screen border area.Normally the total current that flows through the lines for analog powersupply 23 d and the digital power supply line is roughly the same as thecurrent that flow through the line for the GND 24 d, so if the currentthat flows through the line for digital power supply 25 d is extremelysmaller than that of the analog power supply 23 d, the current thatflows through the lines for GND 24 d and the analog power supply 23 dbecome dominant among the current that flows through the source driverIC 101. Therefore it is preferable to make the lines for the GND 24 dand the analog power supply 23 d to be thicker. At the left of the FPC21, the terminal for digital power supply 25 c is provided and isconnected with the source driver IC 101 a at the left. At the right ofthe FPC 21 a, on the other hand, only the terminal for GND 24 c and theterminal for analog power supply 23 c are provided and are connectedwith the source driver IC 101 b at the right. By this, lines for inputprovided in the side section at the right of the FPC 21 a are only twotypes, lines for GND 24 d and analog power supply 23 d, and comparedwith the first embodiment, lines of the GND 24 d and the analog powersupply 23 d can be thicker for the amount of the line for the digitalpower supply 25 d.

[0070] Also according to the present embodiment, in the right sidesection of the FPC 21, the terminal for GND 24 c is disposed at thefurthest outer side, and the terminal for analog power supply 23 c isdisposed at the inner side thereof. At the substrate end side of thesource driver IC 101 b, the bump for GND 1 b is disposed at the furthestleft side, and the bump for analog power supply 2 b is disposed next toit. By this, the line for the GND 24 d, where current flows the most,can be shorter than that for the analog power supply 23 d, which canprevent the deterioration of line resistance. In the side section at theleft of the FPC 21 (source driver IC 101 a side) as well, the terminalfor digital power supply 25 c is provided at the furthest outer sideamong the terminal for digital power supply 25 c, terminal for referencevoltage at the positive polarity side 22 c and terminal for referencevoltage at the negative polarity side 26 c. At the right side of thesource driver IC 101 a as well, the bump for digital power supply 11 ais provided at the furthest right side among the bump for digital powersupply 11 a, bump for reference voltage at the positive polarity side 9a and bump for reference voltage at the negative polarity side 10 a. Bythis, the line for digital power supply 25 d can be shorter than thatfor reference voltage. A drop in the display quality, due to thedeterioration of line resistance, can be prevented by providing thebumps for input for GND and power supply at the outer side of the bumpsfor input for reference voltage at the substrate end side of the sourcedrive IC 101.

[0071] In this way, by disposing the terminal for GND 24 c at thefurthest outer side in the side section of the FPC 21 and disposing thebump for GND 1 at the furthest outer side in the side section of thesource driver IC 101 b, the distance between the terminals and the bumpscan be decreased, and the line length on the glass substrate can bedecreased. As a result, even if the FPC 21 is disposed between thesource driver ICs, a drop of display quality, due to the deteriorationof line resistance, and output errors can be prevented. Also byproviding the terminal where the most current flows at the outer side inthe FPC 21 and is disposed on the source driver IC so as to face thebump for input to be connected with this terminal, the deterioration ofdisplay quality by line resistance can be prevented. In the side sectionof the FPC 21, the terminal for analog power supply 23 c is disposed atthe inner side and next to the terminal for GND 24 c, and on the sourcedrive IC as well. The bump for analog power supply 2 b is provided atthe inner side and next to the bump for GND 1 b. By this, the linelength for the analog power supply 23 d, where the second highestcurrent next to the line for GND 24 d flows, can also be decreased, andline resistance can be decreased.

[0072] Third Embodiment

[0073] The present embodiment will be described with reference to FIG.11. FIG. 11 is a plan view depicting the configuration of the areaaround the bumps for input provided on the source driver IC of theliquid crystal display device. Compared with the first embodiment, theconfiguration between the FPC 21 and the bumps for input is different inthe present embodiment, and description will be omitted for theconfiguration the same as the first embodiment.

[0074] According to the present embodiment, an FPC 21 is mounted atevery other space between the source driver ICs, so that one FPC 21 isconnected to two source driver ICs. This FPC 21 a supplies all thesignals and power for operating both the source driver IC 101 a and thesource driver IC 101 b at the left and right. In other words, terminalsfor connecting with the source driver IC 101 a are provided in the sidesection at the left of the FPC 21, which connect with the respectivebumps for input of the source driver IC 101 a via the line for input onthe glass substrate. In the source driver IC 101 a, the block at theright of the bumps for input is used. In the side section at the rightof the FPC 21, terminals for connecting with the source driver IC 101 bare provided, which are connected with the respective bumps for input ofthe source driver IC 101 b via the lines on the glass substrate. In thesource driver IC 101 b, the block at the left of the bumps for input isused. On the glass substrate, lines for input for GND 24, analog powersupply 23, digital power supply 25, reference voltage at the negativepolarity side 26, and reference voltage at the positive polarity side 22are provided on both the side sections of the FPC. In thisconfiguration, roughly half of the FPCs 21 on the source driver IC 101are connected. By this configuration, the number of connection locationsof the FPC 21 can be decreased to half, so the number of components canbe decreased, and the FPC mounting time for connection can be decreased.As a result, manufacturing cost can be decreased.

[0075] In the side section at the left of the FPC, the terminal for GND24 c, terminal for analog power supply 23 c, and terminal for digitalpower supply 25 c are provided in this sequence from the outer side.This sequence is the sequence of the terminals to which higher currentflows, so the line length can be decreased for the sequence of the linefor GND 24 d, analog power supply 23 d, and digital power supply 25 d.At the inner side of these terminals, the terminal for reference voltageat the negative polarity side 26 c and the terminal for referencevoltage at the positive polarity side 22 c are provided. By providingthe terminals for the GND and the power supply system at the outer sideof the terminals for the reference signal system, the drop of voltage,due to the deterioration of the line resistance, can be minimized.

[0076] Fourth Embodiment

[0077] According to the present embodiment, the FPC 21 is installed atthe substrate end side of the location where the source driver IC 101 isprovided, facing the source driver IC 101, as shown in FIG. 12. In thiscase, the FPC 21 is installed corresponding to each source driver IC101, so the number of source driver ICs 101 and the number of locationswhere the FPC 21 is connected are the same. And the FPC 21 is installedon the glass substrate at the substrate end side of the source driver IC101. For this source driver IC 101, the source driver IC 101, having thebump array shown in FIG. 3, is used, and is connected with the glasssubstrate 27 via the ACF.

[0078] The configuration of the area around the bumps for input will bedescribed with reference to FIG. 13. FIG. 13 is a plan view depictingthe area around the bumps for input provided on the source driver IC ofthe liquid crystal display device. In the present embodiment, the FPC 21is connected near the center of the long side of the source driver IC101. For the connection of the FPC 21 and the GND 24 b, analog powersupply 23 b and digital power supply 25 b, the center block (bump forGND 7 a, bump for analog power supply 6 a, and bump for digital powersupply 8 a) is used in the bumps for input of the source driver IC 101.For the reference voltage, the bump for reference voltage at thepositive polarity side 9 and the bump for reference voltage at thenegative polarity side 5, which are disposed on both sides of thecentral block, are used. On the FPC 21, the terminal for referencevoltage at the positive polarity side 22 a, terminal for analog voltage23 a, terminal for GND 24 a, terminal for digital power supply 25 a, andterminal for reference voltage at the negative polarity side 26 a areprovided from the left in this sequence. At the center of the FPC 21,the terminal for GND 24 a is provided. At the center of the long side102 of the source driver IC 101, the bump for GND 7 a, to be connectedwith the terminal for GND 24 a via the GND 24 b, is provided. Positionsof the bump for GND 7 a and the terminal for GND 24 a are aligned.Therefore the line for the GND 24 b becomes perpendicular to thesubstrate end, and the line length can be decreased compared with otherlines. In the same way, the lines for the digital power supply and theanalog power supply can be made shorter than the lines for the referencevoltage. By this, a drop of display quality, due to the deterioration ofline resistance, can be prevented. By providing bumps for lines wherethe highest current flows, at the center of the long end of the sourcedriver IC, and the terminals of the FPC 21 are provided at the center soas to correspond to these bumps, as described above, a drop of displayquality, due to line resistance, can be prevented.

[0079] In this way, by using a source driver IC according to the presentinvention, both disposing the FPC between the source driver ICs anddisposing it facing the source driver IC becomes possible. By using thesource driver IC having such a bump array, the resistance value can bedecreased in the configuration of the source driver IC, the lines forinput and the FPC 21 on the glass substrate, even if the packaging spaceis restricted. For example, a plurality of source driver ICs 101 caneasily be mounted at equal spacing, so that resistance in the logicsignal line between the source driver ICs can be uniform, and thedisplay quality can be improved. For both the configuration of themounting the FPC between the source driver ICS and the configuration offacing the source driver ICs and FPCs, the same source driver ICs can beused, and the source driver ICs can be common. This can decrease themanufacturing cost of the source driver ICs.

[0080] The pitch of the bumps for input of the source driver IC 101 ismuch smaller than the terminal pitch of the FPC 21. By setting the pitchof the bumps for input to be close to the terminal pitch of the FPC 21,the line length required for making the each line to be perpendicular tothe substrate end can be decreased. The pitch of the bumps for input canbe changed by adjusting the number of bumps provided in the respectivebumps for input shown in FIG. 4. By this, the output errors due to adrop of voltage to the source driver IC can be decreased. Also accordingto the present invention, the FPC is not connected between the sourcedriver ICs, so the space between each source driver IC can be decreased,and the line resistance value of the cascade-connected logic signallines can be decreased, and high-speed transmission of the signals onthe glass substrate becomes possible.

[0081] Other Embodiments

[0082] The present invention is not limited to the above mentionedembodiments, but can be modified in various ways. For example, in theabove mentioned embodiments, the configuration of the lines, bumps andterminals in the reference voltage at the positive polarity side and thereference voltage at the negative polarity side may be reversed. In theembodiments, the current that flows through the line for GND 24 is thehighest, but if the highest current flows through a different line, thenthe bump thereof can be provided at the furthest outer side. In the sameway, the terminal of that line in FPC may be provided to be closest tothe side section. Needless to say, the present invention can be appliednot only to the source driver IC 101 but also to the gate driver IC.

[0083] In the above mentioned embodiments, the number of FPCs is thenumber of locations where the FPC and the glass substrate are connected.In other words, if one FPC is branched outside the glass substrate andconnected to the glass substrate, the number of connection locations isregarded as the number of FPCs. The terminals of the FPC may be at theleft and right sides reversed symmetrically in the configuration. Withthis configuration as well, the line resistance value in line on theglass substrate can be decreased, and logic processing and desiredvoltage can be output normally in the source driver IC. Even if the FPCis connected between the source driver ICs, the line length from thesubstrate end to the center between the source driver ICs can bedecreased, and the line resistance value can be decreased. And bydisposing the clock line at the center of the image data lines, theinfluence of waveform distortion, due to line resistance of the data andclock lines, can be suppressed. Also by packaging the FPC between thesource driver ICs, liquid crystal devices can be manufactured withoutincreasing the panel size.

[0084] According to the present invention, a display device with anarrow screen border area and with excellent display quality can beprovided.

[0085] From the invention thus described, it will be obvious that theembodiments of the invention may be varied in many ways. Such variationsare not to be regarded as a departure from the spirit and scope of theinvention, and all such modifications as would be obvious to one skilledin the art are intended for inclusion within the scope of the followingclaims.

What is claimed is:
 1. A display device, comprising: a display panelcomprising an insulation substrate; a drive circuit disposed around adisplay area on the insulation substrate to output signals to thedisplay panel; a plurality of bumps formed on the drive circuit; and aplurality of lines formed on the insulation substrate and connected withthe bumps, wherein adjacent two or more of the plurality of bumps areelectrically connected on the drive circuit, and the electricallyconnected two or more bumps are connected with one of the lines via ananisotropic conductive film.
 2. A display device according to claim 1,wherein the drive circuit is disposed along an edge of the insulationsubstrate, and the electrically connected bumps are formed substantiallyin parallel with the edge.
 3. A display device according to claim 1,wherein the drive circuit is disposed along an edge of the insulationsubstrate, and the electrically connected bumps are formed substantiallyperpendicular to the edge.
 4. A display device, comprising: a displaypanel comprising an insulation substrate; a plurality of drive circuitsdisposed with a space at an end portion of the insulation substratealong an edge of the insulation substrate to output signals to thedisplay panel; a line section placed at the end portion of theinsulation substrate, between the plurality of drive circuits,comprising external lines for supplying signals or power to theplurality of drive circuits; and a plurality of input lines formed onthe insulation substrate and connected with corresponding lines of theplurality of external lines.
 5. A display device according to claim 4,wherein the external line corresponding to the input line for a highestcurrent flow of the plurality of input lines is placed at a very side ofthe line section.
 6. A display device according to claim 4, wherein thedrive circuit comprises a plurality of bumps for input formed at an edgeside of the insulation substrate along the edge and connected with aline corresponding to the plurality of input lines, and a bump for inputcorresponding to an input line for a highest current flow of theplurality of input lines is placed at an outermost side of the drivecircuit.
 7. A display device according to claim 6, wherein the bumps forinput comprise a bump for GND, a bump for power supply and a bump forreference voltage, the bump for GND and the bump for power supply areplaced as one block at a side section and a center of the drive circuit,and the bump for reference voltage is disposed between blocks.
 8. Adisplay device according to claim 7, wherein the bump for GND and thebump for power supply are electrically connected with the bump for GNDand the bump for power supply in a different block, respectively, in thedrive circuit.
 9. A display device according to claim 7, wherein thebump for GND or the bump for power supply in one block compriseselectrically connected two rows of bumps.
 10. A display device accordingto claim 4, wherein the line section is disposed at every other spacebetween the drive circuits, and the line section is connected with thebumps for input of the drive circuits on both sides.
 11. A displaydevice, comprising: a display panel comprising an insulation substrate;a plurality of drive circuits disposed with a space along an edge of theinsulation substrate to output signals to the display panel; cascadelines formed on the insulation substrate to connect the drive circuitsnext to each other; and a plurality of bumps for cascade line formed onthe drive circuit along a side to a display area and a side to anadjacent drive circuit and connected with the plurality of cascadelines.
 12. A display device according to claim 11, wherein the cascadelines comprise a clock signal line and a plurality of image data signallines, and the clock signal line is disposed between the plurality ofimage data signal lines.
 13. A display device according to claim 11,further comprising bumps for output formed along a side of the drivecircuit close to a display area to output signals to the display panel,wherein the bumps for output or bumps for a cascade line are placed in astaggered fashion.